Background arts concerning the application will be described. Japanese Patent Application No. 2000-178917 (semiconductor device testing method/semiconductor device testing apparatus) discloses a testing method for testing a semiconductor device with high accuracy which outputs a reference clock DQS used for data transfer in synchronization with data reading within a short time.
Japanese Patent Application No. 2000-9113 (semiconductor device testing method/semiconductor device testing apparatus) discloses a testing method for testing a semiconductor device with high accuracy which outputs a reference clock DQS used for data transfer in synchronization with data reading within a short time.
Additionally, Japanese Patent Application No. 2000-204757 (semiconductor device testing method/semiconductor device testing apparatus) discloses a testing method of determining a failure based on a phase difference between a reference clock and data in a semiconductor device which outputs the reference clock in synchronization with data reading and outputting and uses the reference clock for data transfer.
However, since a cross point of the differential clock signals CLK cannot be specified by the background arts, it is impossible to accurately determine PASS/FAIL based on a relative phase difference between the differential clock signal and the other signal.
Next, problems concerning the present invention will be described.
FIG. 6(a) shows a principle circuit connection when high-speed data transfer is executed between two devices on a circuit board or the like in synchronization with a differential clock output as a balanced signal, which is used for differential transmission such as ECL or LVDS.
Differential clock signals CLK (positive clock signal CLKP, negative clock signal CLKN) are output from a differential driver DR1 of a device 1, and supplied through a transmission line to a differential receiver RCV2 of a device 2. One or a plurality of data signals DATA synchronized with a clock are supplied from a flip-flop FF1 of the device 1 to an input terminal of a flip-flop FF2 of the device 2, and retimed by a clock of the differential receiver RCV2 before being used. Incidentally, in the differential clock signal, a variance of output amplitude occurs due to an IC manufacturing variance, phase shifting occurs between differential signals due to circuitry, or other problems occur due to other causes. Further, some jitter components may be contained in the differential clock or the data TADA, or common mode noise may be generated.
Differential clock signals CLK (positive clock signal CLKP, negative clock signal CLKN) are output from a differential driver DR1 of a device 1, and supplied through a transmission line to a differential receiver RCV2 of a device 2. One or a plurality of data signals DATA synchronized with a clock are supplied from a flip-flop FF1 of the device 1 to an input terminal of a flip-flop FF2 of the device 2, and retimed by a clock of the differential receiver RCV2 to be used. Incidentally, in the differential clock signal, a variance of output amplitude occurs due to an IC manufacturing variance, phase shifting occurs between differential signals due to circuitry, or other problems occur. Further, some jitter components may be contained in the differential clock or the data TADA, or common mode noise may be generated.
Thus, in consideration of the foregoing, the device 1 which is a device under test (DUT) is required to output signals based on a prescribed phase relation between a clock and data. A semiconductor test apparatus must be able to determine PASS/FAIL by measuring the output conditions of the differential clock signal and the data DATA based on the prescribed phase relation. Incidentally, the differential driver DR1 can be controlled to a high impedance state by turning off the output. Thus, there is a need to be able to test this driver in the high impedance state.
FIG. 6(b) shows a main portion of the semiconductor test apparatus which comprises a comparator CP used in a single end (unbalanced type) form to receive each of the positive clock signal CLKP and the negative clock signal CLKN that are differential clock signals output from the DUT. Here, the semiconductor test apparatus is constituted such that comparators CP of 2-channel single ends individually receive the differential clock signals output from the DUT because of a need to measure each. For example, a reason is that there is a test item in the high impedance state (Hi-Z mode) of the differential clock signal of the DUT, and there is a need to be able to test this item.
In FIGS. 6a and 6b, the first comparator CP receives one positive clock signal CLKP, and converts the signal into a logical signal at a predetermined threshold level Vref. A timing comparator TC receives the logical signal, and determines PASS/FAIL based on a signal held by a strobe signal STRB of a desired timing.
The second comparator CP receives the negative clock signal CLKN, and converts the clock signal CLKN into a logical signal at a predetermined threshold level Vref. The timing comparator TC receives the logical signal, and determines PASS/FAIL for each single end signal based on a signal held by a strobe signal STRB of a desired timing.
Now, in the case of an ideal differential signal of FIG. 7a, a cross point (point A in FIG. 7a) of clock signals only needs be converted into a logical signal at a threshold level Vref of an intermediate voltage which is ½ of amplitude.
However, as shown in an actual differential signal example of FIG. 7b, if a cross point is converted into a logical signal at a threshold level Vref, it is detected as a cross point (point C in FIG. 7b) shifted from a target cross point (point B in FIG. 7b). Consequently, a problem of a timing shift (difference E in FIG. 7b) occurs between the two cross points, causing accuracy deterioration of timing measurement. Especially, when a clock frequency becomes several hundred MHz or higher, an influence of measuring accuracy is increased. As the semiconductor test apparatus is a measuring device in which highly accurate timing measurement is necessary, this poses a serious practical problem.
FIG. 7c shows a case in which in simultaneous measurement of both signals, i.e., a differential clock signal CLK and a data signal DATA, jitters such as inter-signal interference noise or power supply noise cause an inphase change between the two signals. In this case, an instantaneous relative phase difference Δf between the two signals is small. PASS/FAIL determination must be made to judge whether it is within a normal phase range or not by measuring such an instantaneous phase difference Δf1.
Conversely, FIG. 7d shows a case in which in simultaneous measurement of both signals, i.e., a differential clock signal CLK and a data signal DATA, jitters cause a reversed phase change between the two signals. In this case, an instantaneous relative phase difference Δf between the two signals is increased. PASS/FAIL determination must be made to judge whether it is within a normal phase rage or not by measuring an instantaneous phase difference Δf2 caused by the jitters. Apparently, it is necessary to determine PASS/FAIL by simultaneously measuring the relative phase difference between the two signals.
As described above, the single end comparators CP are applied to the two channels to specify the position of the cross point of the differential clock signals CLK. However, it is impossible to accurately specify the position of the cross point because the phase difference, the amplitude difference or the like between the positive clock signal CLKP and the negative clock signal CLKN causes the movement of the cross point.
To accurately evaluate phases of both signals, i.e., the differential clock signal CLK and the data signal DATA, both signals must be simultaneously sampled and measured, the cross point of the differential clock signals CLK must be specified, and the phases of the specified cross point and the data signal DATA must be evaluated.
However, according to the conventional technology, it is impossible to determine PASS/FAIL by accurately obtaining a relative phase difference between the two signals, i.e., the cross point of the differential clock CLK and the data signal DATA. Because a semiconductor test apparatus is a measuring device in which highly accurate timing measurement is necessary, this poses an unfavorable practical problem.
Therefore, an object of the invention is to provide a semiconductor test apparatus which can realize good device PASS/FAIL determination by using 2-channel single end comparators CP, measuring and specifying a timing of a cross point of differential clock signals output from a DUT, measuring a timing of the other data signal DATA output from the DUT, and obtaining a relative phase difference between the two signals.
Another object is to provide a semiconductor test apparatus which can accurately measure and obtain a cross point of differential clock signals output from a DUT by using 2-channel single end comparators CP.
Another object is to provide a semiconductor test apparatus which can specify a relative phase difference between a differential signal output from a DUT and the other single end signal or differential signal output from the DUT. Another object is to provide a semiconductor test apparatus which can measure relative jitter amounts of a differential signal output from the DUT and the other signal output from the DUT.